| 摘要 |
PURPOSE:To obtain a high-speed element having low gate capacitance by alloying a gate electrode containing the other conduction type impurity formed in a recess (an indentation or a groove) in one conduction type active layer and shaping the other conduction type region in the active layer. CONSTITUTION:A carrier-concentration n-InGaAs layer 2 is grown on an SI-InP substrate 1 as one conduction type active layer. The whole surface of the substrate is coated with an Si3N4 layer 3 as an etching-resistant layer, a gate region is bored to the layer 3, and a recess 4 is formed through recess etching using sulfuric acid, hydrogen peroxide and water as etchants. An Au/Zn/Au layer 5 is applied as a conductive layer containing the other conduction impurity Zn, coating the recess 4. Zn in the Au/Zn/Au layer 5 diffuses to the n-InGaAs layer 2 through heating at 400 deg.C after a lift-off to shape a p<+> type region 6 as the other conduction type region. Ohmic electrodes 7, 8 consisting of Au/AuGe are formed onto the n-InGaAs layer 2 on both sides of a gate electrode, thus completing a FET. Accordingly, source resistance can be reduced by adopting recess structure, and gate capacitance can be minimized.
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