| 摘要 |
PROBLEM TO BE SOLVED: To provide a test pattern generating method in which the time for executing test pattern generating process can be shortened. SOLUTION: A failure is assumed for a logic circuit to be tested (Step S1), a registered undetectable failure is specified among the assumed failures (Step S3), and specifying an object to be processed by removing the specified undetectable failure from the assumed failures and generating a test pattern for the logic circuit by executing simulation for the specified failure (Step S4). |
