发明名称 |
MULTILEVEL CONFIGURABLE LOGIC ANALYZER |
摘要 |
A logic analyzer is provided with probes (20) deriving the signals to be tested which are introduced into a digitizer (22) provided with comparators which carry out a digitization according to a logic system having two states. It comprises a change-over circuit (21) arranged between the probe and the digitizer, which permits associating several or all comparators with a given signal to be tested to extend its digitization to a multi-level logic system. The change-over circuit (21) is constituted by a matrix of MOS transfer gates or field effect transistors (FET's). When the multi-level logic system has at least one medium state limited by two references, the medium state is displayed on a display device (24) according to a straight line or a monotonic curve joining the two references between the beginning and the end of the medium state. When the duration of the medium state exceeds a predetermined duration, the display device (24) is switched on to display the medium state.
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申请公布号 |
US5177483(A) |
申请公布日期 |
1993.01.05 |
申请号 |
US19890367528 |
申请日期 |
1989.06.16 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
BOUTIGNY, PIERRE-HENRI;NGUYEN, HUY A.;RAOULX, DENIS |
分类号 |
G01R13/28;G01R19/165;G01R31/317;G01R31/3177;G06F11/25 |
主分类号 |
G01R13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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