发明名称 Pseudo multiport data memory has stall facility
摘要 A computer memory arrangement comprises a first plurality of input port facilities that are collectively coupled through a first router facility to selectively feed a first plurality of memory modules. It furthermore includes an output port facility that is fed collectively by the first plurality of memory modules. further ,the computer memory arrangement includes an access detection facility for detecting simultaneous and conflicting accesses occurring through more than one of the first plurality of input port facilities for a particular memory,module, and for thereupon allowing only a single one among the simultaneous and conflicting accesses while generating a stall signal for signaling a mandatory stall signal to any request source pertaining to another request.
申请公布号 US7308540(B2) 申请公布日期 2007.12.11
申请号 US20040515453 申请日期 2004.11.22
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V. 发明人 LEIJTEN JEROEN ANTON JOHAN
分类号 G06F12/00;G06F12/06;G06F;G06F13/16;G11C7/10 主分类号 G06F12/00
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