Ultra short transistor fabrication method

摘要

A semiconductor process in which the transistor channel is defined by opposing sidewalls of a pair of masking structures formed on an upper surface of a semiconductor substrate. The spacing between the opposed sidewalls is defined by the thickness of the spacer structure formed between the sidewalls. The thickness of the spacer structure is preferably in the range of approximately 0.04 microns. A masking layer is formed on an upper surface of a semiconductor substrate. The masking layer includes first and second masking structures and a channel trench material. Opposing sidewalls of the first and second masking structures are laterally displaced by a channel displacement. The opposing sidewalls together with an upper surface of the semiconductor substrate define a channel trench. The channel trench is displaced above and aligned with a channel region of the semiconductor substrate. The channel trench material fills the channel trench. A mean projected path characteristic of the channel trench material is less than a mean projected path characteristic of the first and second masking structures. A source/drain impurity distribution is implanted into and through the masking layer to selectively introduce a source/drain impurity distribution into a source/drain region of the semiconductor substrate. The source/drain regions of the semiconductor substrate are laterally displaced on either side of the channel region. The channel trench material is then removed and a gate dielectric layer is formed on the floor of the channel trench. Thereafter, the channel trench is filled with a conductive material to form a conductive gate on the gate dielectric.