发明名称 JUNCTION-ISOLATED VIAS
摘要 A process for forming a junction-isolated, electrically conductive via in a silicon substrate and a conductive apparatus to carry electrical signal from one side of a silicon wafer to the other side are provided. The conductive via is junction-isolated from the bulk of the silicon substrate by diffusing the via with a dopant that is different than the material of the silicon substrate. Several of the junction-isolated vias can be formed in a silicon substrate and the silicon wafer coupled to a second silicon substrate comprised of a device that requires electrical connection. This process for forming junction-isolated, conductive vias is simpler than methods of forming metallized vias, especially for electrical devices more tolerant of both resistance and capacitance.
申请公布号 WO2006093938(A2) 申请公布日期 2006.09.08
申请号 WO2006US07032 申请日期 2006.02.27
申请人 ENDEVCO CORPORATION;WILNER, LESLIE, B. 发明人 WILNER, LESLIE, B.
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