| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a flash memory device that is decreased in chip area, and has bit line bias and bit line coupling formed in an array area by using low-voltage transistors, and an operation method of the device. <P>SOLUTION: The nonvolatile memory device includes wells in a first conduction type formed in a substrate, and a plurality of first memory cell transistors connected in series to bit lines formed in the wells. Buffers are formed outside the wells on the substrate, and connected to the bit lines. At least one decoupling transistor, which is formed so as to separate the buffers from the bit lines, is formed in the well. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
