发明名称 |
CENTRAL PROCESSOR UNIT HAVING SIMULATIVE INTERPRETATION CAPABILITY |
摘要 |
An electronic digital computer provides real time simulation of the operation of a different digital computer with a minimal amount of special interpretive software. The central processor of the simulating computer develops and stores in one register the memory address of the operands processed by the program being interpreted. In another register, the simulating processor develops and stores the memory address of an interpretive subroutine for each instruction of the program being interpreted. The simulating computer in addition operates a third central processor register as an effective program counter during execution of simulative interpretation. A fourth register is used to supply the memory sector portion of the memory addresses developed above. Each of the four registers is directly accessible by other elements of the central processor.
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申请公布号 |
US3698007(A) |
申请公布日期 |
1972.10.10 |
申请号 |
USD3698007 |
申请日期 |
1970.11.30 |
申请人 |
HONEYWELL INC. |
发明人 |
RONALD D. MALCOLM;WILLIAM J. PHELAN;THOMAS L. SANGIOLO |
分类号 |
G06F9/455;(IPC1-7):G05B19/18 |
主分类号 |
G06F9/455 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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