| 摘要 |
PURPOSE:To provide the titled semiconductor storage device with an interface control function and a buffer memory function by storing input data in a specified address of the storage device and successively outputting data from an address specified by a reading address circuit. CONSTITUTION:Writing and reading address counters WAC, RAC successively specify writing and reading addresses based on respective timing signals phiwc, phirc outputted from a timing control circuit TC. The writing and reading address signals are supplied to an address selecting circuit ASL and an address comparator AC. When an inner control signal r/w,ref is received from the circuit TC, the circuit ASL alternatively selects the writing and reading signals, supplies a complementary address signal to row and column address decoders RDCR, CDCR, and when the signal ref is 'L' and the signal r/w is 'H', writes data successively in a M-ARY 0. When writing and reading addresses coincide with each other, the circuit AC turns an address full signal af to 'H' and sends the data to a reading printer PRT.
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