发明名称 INTEGRIERTE SCHALTUNG IN KOMPLEMENTAERER SCHALTUNGSTECHNIK MIT EINEM SUBSTRATVORSPANNUNGS-GENERATOR.
摘要 One or more FETs (T1) of a first channel type is arranged in a dopded semiconducting substrate (1) of a first conductor type. One or more FETs (T2) of a second type is arranged in a tub-shaped zone (2) of a second conductor type in the substrate. The zone is connected to a supply voltage (VDD) and the substrate to a bias voltage generator (16). The Pn junction between the earthed connection of the first FET and the substrate is reverse biassed. The substrate bias voltage generator (16) output (17) is connected to the earth point via an electronic switch (S1) which is controlled by that output (17). The bias generator (16) may be integrated in the semiconducting substrate (1).
申请公布号 DE3681540(D1) 申请公布日期 1991.10.24
申请号 DE19863681540 申请日期 1986.08.04
申请人 SIEMENS AG, 8000 MUENCHEN, DE 发明人 TAKACS, DIPL.-PHYS., DEZSOE, W-8000 MUENCHEN 83, DE;WINNERL, DR.-ING., JOSEF, W-8300 LANDSHUT, DE
分类号 H01L27/10;G05F3/20;H01L21/822;H01L21/8234;H01L21/8238;H01L27/04;H01L27/08;H01L27/088;H01L27/092;H01L29/78;(IPC1-7):G05F3/20 主分类号 H01L27/10
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