| 摘要 |
A pseudo-noise sequence generator includes a memory (10) which is accessed by a (2n+m)-bit address signal and outputs a parallel n-bit pseudo-noise sequence prestored at a corresponding address, and n registers (111, 112,...,11n) for delaying each bit of the parallel n-bit output signal from the memory (10) by one clock. The (2n+m)-bit address signal consists of a parallel n-bit digital input signal, the outputs from the n registers, and a m-bit control signal. |
