| 摘要 |
<p>A control circuit for slowly turning off a solid-state power transistor, particularly for inductive loads, comprising means (R1,R2,18) for limiting the load current flowing through the switch, and timing and control circuits (19,6,11,12,13) to ensure, irrespective of the duration of a command pulse, slowed turn-off of the switch with a predetermined delay as to the time when the maximum load current value is reached, thereby keeping the power dissipation through the switch during the load current limiting phase within predetermined values and the turn-off overvoltage within predetermined levels. <IMAGE></p> |
