| 摘要 |
PURPOSE:To reduce data error to the phase fluctuation of input data by optimumly setting the phase amount of the input data for a frame aliner based on an output timing signal in the case of reading out the data from a storing means and an inputted frame signal. CONSTITUTION:When it is desired to operate a control means 4, a control signal to be inputted from an external part is set in an active state. A latch circuit 4b latches the counted value of a down counter 4a corresponding to a latch timing signal. The value is applied to a shift register 3 as a shift amount. After determining the shift amount of the shift register 3, the control signal is turned to an inactive state and a gate circuit 4c is turned to a disable state. Accordingly, even when the phase of the input data is fluctuated after once determining the shift amount, the phase of the frame in the data written to the frame of read data can be kept optimum. |
