发明名称 LOAD-BALANCED SWITCH ARCHITECTURE FOR REDUCING CELL DELAY TIME
摘要 A switch apparatus is provided with a plurality of input interfaces, a plurality of intermediate buffers; a plurality of output interfaces; an input-side switch providing connections between the input interfaces and the intermediate buffers; and an output-side switch providing connections between the intermediate buffers and the output interfaces. Each of the plurality of input interfaces is provided with a plurality of pointers for each of the output interfaces, each of the plurality of pointers containing a pointer value indicating one of the intermediate buffers. The plurality of input interfaces are each designed to select one of the plurality of pointers and to forward arriving cells to desired ones of the plurality of intermediate buffers starting from selected one of the plurality of intermediate buffers in response to a pointer value contained in the selected one of the plurality of pointers.
申请公布号 US2008031262(A1) 申请公布日期 2008.02.07
申请号 US20070833835 申请日期 2007.08.03
申请人 NEC CORPORATION 发明人 NISHIZAKI HIDEKI;YAMADA KENSHIN
分类号 H04L12/56 主分类号 H04L12/56
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