| 摘要 |
<p>A decimation filtering circuit (300) for performing a decimation operation with a decimation factor of M in a pipeline structure. A finite impulse response ('FIR') filtering of N taps for achieving a desired frequency response is designed to have an integral ratio of N/M. A total of N/M processing stages (301, 302) is connected in series to accumulate filtered data based on data samples of an input signal and predetermined FIR coefficients. Each of the N/M processing stages (301, 302) produces an accumulated output in every other M accumulations for M input data samples.</p> |
