Avalanche programmed floating gate memory cell structure with program element in first polysilicon layer

摘要

A non-volatile memory cell structure which includes a floating gate, at least one injection element and a sense transistor. The injection element is at least partially formed in a first polysilicon layer. The floating gate is provided in a second polysilicon layer and capacitively coupled to the reverse breakdown element. The sense transistor is at least partially formed in a region of a semiconductor substrate, and connected to the floating gate. The structure may further comprise a control gate capacitively coupled to the floating gate and may be formed in said first polysilicon layer.