发明名称 Testing integrated circuits
摘要 The specification describes a technique for burn-in electrical testing of IC dies prior to wire bonding the dies to the next interconnection level. The dies are provided with a test solder bump array interconnected to the IC contact pads of the dies. The Known Good Dies (KGD) can then be wire bonded, or alternatively flip-chip solder bump bonded, to the next interconnect level. <IMAGE>
申请公布号 EP1098363(A2) 申请公布日期 2001.05.09
申请号 EP20000309584 申请日期 2000.10.30
申请人 LUCENT TECHNOLOGIES INC. 发明人 DEGANI, YINON
分类号 G01R31/26;H01L21/60;H01L21/607;H01L21/66;H01L23/485 主分类号 G01R31/26
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