Digital phase locked loop circuitry and methods

摘要

Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

主权项

1. Apparatus for converting parallel data to serial data, the apparatus comprising:
serializer circuitry for:
receiving, at a first clock rate, the parallel data; andoutputting, at a second clock rate, each bit of the parallel data, one bit after another in succession; and circuitry for replicating each bit that is output by the serializer onto a number of parallel leads, wherein the number is based on a ratio of the first clock rate and the second clock rate.