发明名称 DATA PROCESSING DEVICE
摘要 PURPOSE:To cope efficiently with a request of a large quantity of continuous memories and a request of memory extension by providing a means for securing a necessary memory area by coupling plural memory area pieces on a main memory. CONSTITUTION:When it is decided by a controlling circuit 6 that an instruction code stored in an instruction register 7 is a memory access instruction, an A1 field of an operand of the instruction register 7 is stored in an address register 2, and an A2 field is stored in a register 21 of a differential circuit 3 through a data bus 37. The controlling circuit 6 reads out a main memory 1 by using a value stored in the address register 2 as an address. The read-out contents of the main memory consist of an Li part for showing the length of a memory area and an Ri part having an address of the next continuous memories, and the Li is stored temporaily in a buffer register 4 through a bus 38, and sent to the differential circuit 3 in order to be compared with an operand part of the memory access instruction stored in the register 21. The Ri is stored in the address register 2 for the purpose of preparation for executing access to the next memory area.
申请公布号 JPS60132241(A) 申请公布日期 1985.07.15
申请号 JP19830240333 申请日期 1983.12.20
申请人 NIPPON DENKI KK 发明人 SHIMAZU HIDEO
分类号 G06F9/44;G06F9/30;G06F12/00;G06F12/02 主分类号 G06F9/44
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