| 摘要 |
A wafer-scale semiconductor memory device includes a wafer (1), and a plurality of memory chips (2) formed on the wafer. The memory chips contain a memory chip which includes a storage circuit (11, 21), and a switching transistor (QA) which selectively connects the storage circuit to a power supply line (Vcc) in response to a control signal (G, G1). The memory chip also includes a control logic circuit (12; 22, 24) which writes data into the storage circuit and reads out data from the storage circuit and which generates a logic signal used for controlling the transistor. Further, the memory chip includes a fail-safe circuit (13, 23, 23A) having a circuit element (F, G) having a status showing whether or not the control logic circuit is malfunctioning. The fail-safe circuit generates the control signal from the logic signal and the status of the circuit element so that when the circuit element has the status showing that the control logic circuit is malfunctioning, the fail-safe circuit outputs the control signal which instructs the switching element to disconnect the storage circuit from the power supply line irrespective of the logic signal. <IMAGE> |
