Enhanced flash chip and method for packaging chip

摘要

An enhanced Flash chip and a method for packaging chip, wherein the enhanced Flash chip comprising: a FLASH and a RPMC, packaged integrally; the FLASH and the RPMC each comprising: a first internal IO pin and a second internal IO pin; the FLASH and the RPMC being further provided with a jumper window, one end of which is mutually connected to the first internal IO pin of the FLASH or the RPMC and the other end of which is mutually connected to the first internal IO pin of the RPMC or the FLASH; the second internal IO pin of the FLASH and the second internal IO pin of the RPMC being mutually connected. The enhanced Flash chip provided in the present application may effectively reduce design complexity and chip manufacturing cost, avoid the crossing of the metal lead wires in the chip package, and increase the yield of chip packages.

主权项

1. An enhanced Flash chip, comprising:
a FLASH and a Replay Protection Monotonic Counter, RPMC, which are packaged integrally; wherein, the FLASH comprises an independent controller and the RPMC comprises an independent controller respectively; the same IO pins in the FLASH and in the RPMC are mutually connected, and are connected to same external sharing pins of the enhanced Flash chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pins of the enhanced Flash chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; the FLASH further comprises a first internal IO pin and a second internal IO pin and the RPMC further comprises a first internal IO pin and a second internal IO pin, respectively; the FLASH is further provided with a jumper window, one end of which is mutually connected to the first internal IO pin of the FLASH and the other end of which is mutually connected to the first internal IO pin of the RPMC, or the RPMC is further provided with a jumper window, one end of which is mutually connected to the first internal IO pin of the RPMC and the other end of which is mutually connected to the first internal IO pin of the FLASH; and wherein the second internal IO pin of the FLASH and the second internal IO pin of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected the first internal IO pins and the second internal IO pins.