Techniques for Determining Local Interconnect Defects

摘要

Techniques are presented for the determination defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defective blocks, a reference current is determined based on the amount of current drawn by the local interconnects when a high voltage is applied and all of the blocks are de-selected. The amount of leakage current is determined when a selected block is biased to ground and the high voltage is applied to the interconnects. By comparing the reference current to the leakage current, a determination can be made on whether the selected block has defects related to the local interconnect structure.

主权项

1. A method of determining defects in a monolithic three-dimensional semiconductor memory device having an array of memory cells arranged in multiple physical levels above a silicon substrate and including a charge storage medium, the memory cells being formed into a plurality of blocks each having a plurality of NAND strings, wherein the NAND strings are formed above a well structure and run in a vertical direction relative to the substrate and are formed in groups between local interconnect lines that also are formed above the well structure and run in the vertical direction relative to the substrate, and wherein the local interconnect lines are connected along global interconnect lines that run in a horizontal direction relative to the substrate, the method comprising:
performing a reference current level determination, including:
biasing the array by deselecting the blocks and applying a high voltage along the global interconnect lines, and determining the reference current level from an amount of current drawn by the global interconnect lines with the array is so biased; performing a leakage current level determination, including:
biasing the array by setting elements of a selected block to ground and applying the high voltage along the global interconnect lines, and determining the leakage current level from an amount of current drawn by the global interconnect lines with the array is so biased; performing a comparison of the leakage current level with the reference current level; and based upon the comparison, determining whether the selected block has an associated defect.