| 摘要 |
Logic circuitry converts binary intelligence into a first amplitude for a binary "1" and a second amplitude for a binary "O." This same logic circuitry converts a frame timing signal into a third amplitude half way between the first and second amplitudes. These three amplitudes are converted into, for instance, three distinct frequencies with the frequency corresponding to the third amplitude being disposed half way between the frequencies corresponding to the first and second amplitudes. After transmission, the three amplitudes are recovered. A first voltage comparator having a reference voltage equal to the third amplitude recovers the binary intelligence from which a local clock is generated with the local clock pulses being delayed to be centered in the binary digits. A pair of voltage comparators having reference voltages straddling the third amplitude, but less than the first amplitude and greater than the second amplitude and a sampling gate responding to the outputs of the pair of voltage comparators and the local clock pulses recover the frame timing signal to enable frame synchronization of the receiver with the transmitter.
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