All-digital spread spectrum clock generating circuit with EMI reduction effect and a method for controlling the same

摘要

An all-digital spread spectrum clock generating circuit with EMI reduction effect and a method for controlling the same utilize a digital spread-spectrum clock controlling unit to control a digital controlled oscillator, so that it can directly modulates an output clock frequency. Accordingly, the spectrum of the output clock frequency is spread, and the EMI effect due to the output clock signal is reduced. A spread-spectrum clock controller receives a reference clock counting signal and a dividing clock counting signal generated by a frequency detecting unit. After detecting and judging, the spread-spectrum clock controlling unit modulates and maintains a central frequency of the spread-spectrum clock periodically according to the two counting signals, thereby keeping a stability of the central frequency of the spread-spectrum clock signal and decreasing the complexity of the circuit design.

主权项

1. An all-digital spread spectrum clock generating circuit with EMI reduction effect comprising:
a spread-spectrum clock controlling unit that receives and generates a delta-sigma modulator control signal according to at least one phase and frequency detecting signal, a reference clock counting signal, and a dividing clock counting signal; a phase frequency detecting unit that receives and detects a reference clock signal and a dividing clock signal so as to correspondingly generate said phase and frequency detecting signal; a digital controlled oscillator that generates an output clock signal according to said-a delta-sigma modulator control signal; a dividing unit that is coupled to said digital controlled oscillator and receives said output clock signal so as to divide said output clock signal and generate a dividing clock signal; and a frequency detecting unit that receives said dividing clock signal and said reference clock signal so as to generate said reference clock counting signal and said dividing clock counting signal according to said dividing clock signal and said reference clock signal; said spread-spectrum clock controlling unit adjusting a central frequency of said output clock signal according to said reference clock counting signal and said dividing clock counting signal, wherein, said spread-spectrum clock controlling unit reads and compares counting results of said reference clock counting signal and said dividing clock counting signal; if said counting result of said reference clock counting signal is larger than said counting result of said dividing clock counting signal, said spread-spectrum clock controlling unit allows said output clock signal to increase the clock frequency; if said counting result of said dividing clock counting signal is larger than said counting result of said reference clock counting signal, said spread-spectrum clock controlling unit allows said output clock signal to decrease said clock frequency.