| 摘要 |
PROBLEM TO BE SOLVED: To provide a data buffer monitor circuit which can securely detect trouble occurring in a write address generating circuit and a read address generating circuit in such a case. SOLUTION: Input data from an input terminal 1 are stored in a data storage part 4a of a storage circuit 4, and input parity corresponding to the input data is generated by a parity generating circuit 7, delayed by >=1 bit through a write address delay circuit 8, and stored in a parity storage part 4b of the storage part 4a. Further, the data stored in the data storage part 4a are read out and outputted to an output terminal 2, and delayed by >=1 bits through the write address delay circuit 8, and a parity matching circuit 11 compares the parity generated by the parity generating circuit 10 with the parity read out of the parity storage part 4b and outputs the parity comparison result from a comparison result output terminal 3. |
