| 摘要 |
<p>PURPOSE:To increase the value of N (the number of outputs of multi-phase clocks by adding a shift register and at the same time to decrease the value of N by giving a certain order bit of the outputs of the shift register to an OR gate. CONSTITUTION:A reset signal is set at a high level and is also used to a clear input of a shift register 5 to clear all bits of the output of the register 5. At the same time, an FF3 is set via an OR gate 4, and the output of the gate 4 is set at a high level. Therefore, the series input of the register 5 is set at a high level. When the reset signal is set at a low level, the first bit of the register 5 is set by the first clock that is supplied to the register 5. Then the output of the register 5 is set at a high level, and the FF3 is reset. Therefore the first bit of the register 5 is reset by the next clock, and the output of the register 5 is set at a low level. The clocks are successively supplied, and the N-th bit of the register 5 is set at a high level. Then the FF3 is set again. Then the first bit of the register 5 is set again, and the output of the register 5 is set again at a high level.</p> |
