Adapter for interconnecting single-ended and differential SCSI buses to prevent 'busy' or 'wired-or' glitches from being passed from one bus to the other

摘要

A SCSI adapter for interconnecting first and second SCSI buses includes a filter for preventing BUSY glitches from being passed from one bus to the other. The filter includes a shift register connected to NAND logic. The SCSI adapter also has a circuit for establishing a desired timing relationship between DATA signals received over the first bus and corresponding ACK or REQ signals also received over that bus that indicate whether the DATA signals are valid. The circuit includes a DATA latch responsive to a delayed version of the ACK or REQ signal received at a clock input thereof. The output of the latch and the corresponding delayed ACK or REQ are transmitted over the second bus.