发明名称 TIMING GENERATING CIRCUIT
摘要 PURPOSE:To generate plural different timing pulses with the same circuit by combinations of processing instructions by using an address counter having a function to interpret instructions in order to access a memory in which logical information is stored. CONSTITUTION:An address counter 1 having the function to interpret instructions outputs the output therefrom to the address line 2 of a memory 3 in which the processing instructions are stored. The index data as the output from the memory 3 is transferred through an index data line 5 to an instruction processing circuit 9 and a data selecting circuit 11. The data on the processing instruction is transferred through a processing instruction data line 6 to an instruction register 7. Processing is performed in the address counter by, for example, three kinds of instructions; NOP, LOOP and JUMP, and the timing data is outputted to a timing output 4. Then the less number of memories is required as compared to the conventional method using a specified sequence.
申请公布号 JPS59160775(A) 申请公布日期 1984.09.11
申请号 JP19830034425 申请日期 1983.03.04
申请人 OKI DENKI KOGYO KK 发明人 OOTAKI MIKIO
分类号 G01R31/28;G01R31/319;G06F11/273;(IPC1-7):G01R31/28 主分类号 G01R31/28
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