发明名称 LOGIC VERIFICATION METHOD
摘要 PROBLEM TO BE SOLVED: To generate a varied large-scale test command sequence by a method arbitrarily combining plural small-scale unit command sequences, different from a conventional large-scale test command sequence-generating method requiring a complicated automatic command generation process for realizing a varied large-scale test because contents of the test command sequence are poor on account of difficulty of generation algorithm. SOLUTION: This logic verification method comprises an automatic command generation process for deciding combination of commands according to previously given conditions or arbitrary conditions, and generating the plural command sequences (hereinafter referred to as command blocks) by the combined commands; and an automatic test command generation process for selecting specific command blocks from the plural command blocks according to the given conditions or the arbitrary conditions, and combining and executing the selected command blocks.
申请公布号 JP2002157145(A) 申请公布日期 2002.05.31
申请号 JP20000357625 申请日期 2000.11.20
申请人 HITACHI LTD 发明人 KAMIMURA KENGO;MITSUMATA HIROICHI;KODAMA YUTAKA
分类号 G06F12/08;G06F11/28 主分类号 G06F12/08
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