发明名称 |
MULTIPROCESSOR SYSTEM AND INTERRUPT ARBITER THEREOF |
摘要 |
In a tightly coupled multiprocessor system, I/O interrupts are distributed to respective processors in accordance with load conditions of the processors. Interrupt arbitration circuits provided in respective processors receive an interrupt request from an I/O device, effect interrupt arbitration using a parameter indicating the load condition of each processor as a first interrupt priority PPR. If the arbitration fails to determine a sole processor, additional arbitration finally selects a sole processor on the basis of the second interrupt priority RRPR which is variable circularly.
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申请公布号 |
CA2061127(C) |
申请公布日期 |
1996.12.03 |
申请号 |
CA19922061127 |
申请日期 |
1992.02.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MUNEHIRO, FUKUDA;NOBUYUKI, OOBA;TAKEO, NAKADA |
分类号 |
G06F9/48;G06F9/50;G06F13/24;G06F13/26;G06F13/362;(IPC1-7):G06F9/46;G06F15/16 |
主分类号 |
G06F9/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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