Closed loop clock signal generator with multiple reference clocks

摘要

A system may include a processor, a first clock source generating a first clock signal, a second clock source generating a second clock signal, and a clock generation unit. In a first closed-loop mode of operation, the clock generation unit may be configured to generate a system clock signal at a target frequency by comparing the system clock signal to the first clock signal. The clock generation unit may be configured to generate the system clock signal in an open-loop mode of operation in response to a transition in a control signal. The clock generation unit may be configured to operate in a second closed-loop mode of operation after operating in the open-loop mode of operation, wherein the clock generation unit is configured to generate the system clock signal at substantially the same target frequency by comparing the system clock signal to the second clock signal.

主权项

1. A system, comprising:
a processor, wherein at least a portion of the processor is clocked by a system clock signal; a first clock source configured to generate a first reference clock signal; a second clock source configured to generate a second reference clock signal; wherein a frequency of the second reference clock signal is lower than a frequency of the first reference clock signal; and a clock generation unit configured to:
operate in a first closed-loop mode of operation, wherein the clock generation unit is configured to generate the system clock signal at a target frequency by comparing the system clock signal to the first reference clock signal during the first closed-loop mode of operation;generate the system clock signal in an open-loop mode of operation in response to a transition in a control signal; andoperate in a second closed-loop mode of operation after operating in the open-loop mode of operation, wherein the clock generation unit is configured to generate the system clock signal at substantially the same target frequency by comparing the system clock signal to the second reference clock signal during the second closed-loop mode of operation.