发明名称 Systems and methods for dimming control with capacitive loads
摘要 System and method for dimming control. The system includes a system controller including a first controller terminal and a second controller terminal, a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, and a resistor including a first resistor terminal and a second resistor terminal. The system controller is configured to generate a first signal at the first controller terminal based on an input signal and to generate a second signal at the second controller terminal based on the first signal. The first transistor terminal is coupled to the second controller terminal. The first resistor terminal is coupled to the second transistor terminal. The second resistor terminal is coupled to the third transistor terminal. The transistor is configured to receive the second signal at the first transistor terminal and to change between two conditions in response to the second signal.
申请公布号 US9414455(B2) 申请公布日期 2016.08.09
申请号 US201414562432 申请日期 2014.12.05
申请人 On-Bright Electronics (Shanghai) Co., Ltd. 发明人 Zhou Jun;Xiong Zhongliang;Li Miao;Cao Yaming;Luo Qiang;Fang Lieyi
分类号 H05B37/02;H05B33/08 主分类号 H05B37/02
代理机构 Jones Day 代理人 Jones Day
主权项 1. A system for dimming control, the system comprising: a system controller including a first controller terminal and a second controller terminal; a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal; and a resistor including a first resistor terminal and a second resistor terminal; wherein: the system controller is configured to generate a first signal at the first controller terminal based at least in part on an input signal and to generate a second signal at the second controller terminal based at least in part on the first signal;the first resistor terminal is coupled to the second transistor terminal;the second resistor terminal is coupled to the third transistor terminal; andthe transistor is configured to receive the second signal at the first transistor terminal and to change between a first condition and a second condition in response to the second signal; wherein: the first signal is at a first logic level during a first period of time and changes between the first logic level and a second logic level during a second period of time, the second period of time including a third period of time and a fourth period of time;the second signal keeps at the second logic level during the first period of time and the third period of time; andthe second signal changes from the second logic level to the first logic level after the third period of time and remains at the first logic level during the fourth period of time.
地址 Shanghai CN