| 摘要 |
PROBLEM TO BE SOLVED: To miniaturize circuit scale without lowering performance by providing information, which shows a frame to be inputted, without omission at the rate of internal clock, which is generated asynchronously while making its frequency different from that of clock signal synchronized with that frame, through a RAM having a single accessible port. SOLUTION: An input synchronizing means 12 synchronizes a frame with a frame stream, counts a clock signal and generates the write address and RW identification information of RAM 11 having the single accessible port. An internal synchronizing means 13 generates the read address of RAM 11 by counting an internal clock signal generated asynchronously with the clock signal. Corresponding to the RW identification information, an address selecting means 14 alternately selects the write and read addresses and reads the RAM 11. As a result, a retiming means 17 performs retiming to information held by a reading means 16. Thus, rate conversion is enabled in small circuit scale. |
