Systems and methods for queue level SSL card mapping to multi-core packet engine

摘要

The present invention is directed towards systems and methods for distributed operation of a plurality of cryptographic cards in a multi-core system. In various embodiments, a plurality of cryptographic cards providing encryption/decryption resources are assigned to a plurality of packet processing engines in operation on a multi-core processing system. One or more cryptographic cards can be configured with a plurality of hardware or software queues. The plurality of queues can be assigned to plural packet processing engines so that the plural packet processing engines share cryptographic services of a cryptographic card having multiple queues. In some embodiments, all cryptographic cards are configured with multiple queues which are assigned to the plurality of packet processing engines configured for encryption operation.

主权项

1. A method of assigning a plurality of Secure Socket Layer (SSL) cards to a plurality of packet processing engines in a multi-core device, the method comprising:
(a) receiving, by a card distribution manager of a multi-core device, identification of a plurality of packet processing engines configured to operate on a respective core of the multi-core device and one or more Secure Socket Layer (SSL) cards of the multi-core device; (b) establishing, by the card distribution manager, a plurality of queues for each of the one or more SSL cards; (c) copying, corresponding to the established plurality of queues, a first user space memory allocation of a first SSL card of the one or more SSL cards, to establish at least a second user space memory allocation; and (d) allocating, by the card distribution manager, the first user space memory allocation and a first queue of the plurality of queues of the first SSL card to a first packet processing engine of the plurality of packet processing engines, and the second user space memory allocation and a second queue of the plurality of queues of the first SSL card to a second packet processing engine of the plurality of packet processing engines.