发明名称 Digital signal processor prefetch buffer and method
摘要 A prefetch buffer and prefetch method. In one embodiment, the prefetch buffer has a main buffer embodied as a direct-mapped cache, and the prefetch buffer includes: (1) an alias buffer associated with the main buffer and (2) a prefetch controller associated with the main buffer and the alias buffer and operable to cause the alias buffer to store potentially aliasing cachelines of a loop body instead of the main buffer.
申请公布号 US9348590(B1) 申请公布日期 2016.05.24
申请号 US201314019633 申请日期 2013.09.06
申请人 VERISILICON HOLDINGS CO., LTD. 发明人 Kashyap Asheesh;Nguyen Tracy
分类号 G06F9/30;G06F9/38;G06F12/08 主分类号 G06F9/30
代理机构 代理人
主权项 1. A prefetch buffer having a main buffer embodied as a direct-mapped cache, said prefetch buffer comprising: an alias buffer associated with said main buffer; a prefetch controller associated with said main buffer and said alias buffer and operable to cause said alias buffer to store potentially aliasing cachelines of a loop body instead of said main buffer; and a protect register associated with said prefetch controller and operable to store cacheline protect bits for said main buffer, a corresponding protect bit set to protect a cacheline from being overwritten if said loop body is smaller than said main buffer.
地址 Plano TX US