发明名称 Phase-lock loop and Miller decoder employing the same
摘要 A phase-lock loop is disclosed for synchronizing an oscillator signal with a train of input signal pulses, some of which may be missing. The phase-lock loop is of particular use in a decoder for decoding digitally encoded data employing a self-clocking coding scheme. The decoder generates a clock from the input signal stream for use in the decoding process.
申请公布号 US4456884(A) 申请公布日期 1984.06.26
申请号 US19810321542 申请日期 1981.11.16
申请人 SRI INTERNATIONAL 发明人 YARBOROUGH, JR., JOHN M.
分类号 H03M5/04;G11B20/14;H03L7/14;H03L7/181;H03L7/199;H04L7/033;H04L25/49;(IPC1-7):H03K13/24;H03L7/18 主分类号 H03M5/04
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