Reducing power consumption in a fused multiply-add (FMA) unit of a processor

摘要

In one embodiment, the present invention includes a processor having a fused multiply-add (FMA) unit to perform FMA instructions and add-like instructions. This unit can include an adder with multiple segments each independently controlled by a logic. The logic can clock gate at least one segment during execution of an add-like instruction in another segment of the adder when the add-like instruction has a width less than a width of the FMA unit. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a core including a plurality of execution units to execute instructions, the plurality of execution units including a fused multiply-add (FMA) unit to perform FMA instructions and add-like instructions, the FMA unit including a multiplier and an adder coupled to an output of the multiplier, the adder of a width having a plurality of segments each independently controllable to be powered on or off, and a tracker coupled to the adder to cause all segments of the adder to be powered on during execution of a first instruction in the FMA unit following a FMA instruction, wherein the first instruction is not to use the all segments of the adder, and otherwise to cause a corresponding segment to be powered on only if the segment is to be used during execution of an instruction.