发明名称 |
Reconfigurable semiconductor device |
摘要 |
A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in accordance with an operation switch signal. |
申请公布号 |
US9425798(B2) |
申请公布日期 |
2016.08.23 |
申请号 |
US201314375344 |
申请日期 |
2013.02.14 |
申请人 |
TAIYO YUDEN CO., LTD. |
发明人 |
Satou Masayuki;Sato Koshi |
分类号 |
G01R31/02;G01R31/26;H03K19/177;G11C29/00;G06F7/38;G11C11/34;G11C8/10;G11C7/00 |
主分类号 |
G01R31/02 |
代理机构 |
Chen Yoshimura LLP |
代理人 |
Chen Yoshimura LLP |
主权项 |
1. A semiconductor device capable of reconfiguration, comprising:
a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in accordance with an operation switch signal. |
地址 |
Tokyo JP |