发明名称 FREQUENCY GENERATOR CIRCUIT
摘要 PROBLEM TO BE SOLVED: To perform a stable operation of a PLL circuit even while reducing the number of parts. SOLUTION: A comparison frequency (b) outputted from a frequency divider 2 is controlled so as to be X times as long as a channel interval dF by making the frequency-diving number R in the frequency divider 2 to be R=a/(dF×X) (X is a natural number) and also making the denominator of the frequency diving number to be X in a fraction frequency divider 8 at the time when a receiving station transmission frequency signal is generated in the case a reference frequency outputted from a reference oscillator 1 is defined as (a) and the channel interval is defined as dF, the comparison frequency (b) outputted from the frequency divider 2 is also controlled so as to be b=dF×X×(K+1)/K by making the frequency dividing number R in the frequency divider 2 to be R=a(K+1)/(dF×K×X) and also making the denominator of the frequency dividing number to be X in the fraction frequency divider 8 in the case the frequency dividing number is defined as K in a frequency divider 9 when a transmission carrier wave frequency signal is generated, and the current of a charge pump 4 is further controlled so as to be (K+1)K times as high as the current at the time when the receiving station transmission frequency signal is generated.
申请公布号 JP2002164784(A) 申请公布日期 2002.06.07
申请号 JP20000361133 申请日期 2000.11.28
申请人 NEC SAITAMA LTD 发明人 USUI HISAYOSHI
分类号 H03L7/197;H03L7/08;H03L7/183 主分类号 H03L7/197
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