Equalizer and semiconductor memory device including the same

摘要

Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.

主权项

1. A memory device comprising:
a first driver circuit configured to output one or more output signals on an output node of the first driver circuit or float the output node based on one or more first driver select signals; and a second driver circuit configured to amplify or store the one or more output signals in response to a second driver select signal, wherein the second driver circuit includes: a first circuit including an input node connected to the output node of the first driver circuit, the first circuit configured to selectively output a delay signal delaying a first output signal of the one or more output signals applied to the input node of the first circuit or an inverted signal inverting the first output signal of the one or more output signals in response to the second driver select signal, and a second circuit including an input node connected to an output node of the first circuit and an output node connected to the output node of the first driver circuit, the second circuit configured to invert an output signal of the first circuit.