发明名称 |
Semiconductor memory having sub-word line replacement |
摘要 |
In a semiconductor memory apparatus having a row decoder classified by main word lines and word lines, the number of spare lines for a defect is increased without increasing the number of spare main word lines. The area of a redundancy circuit is minimized to improve the yield of chip. Normal and spare memory blocks each including a plurality of memory cells are each divided so that replacement may be effected without increasing the number of spare main word lines even when defective addresses associated with a plurality of normal main word lines take place.
|
申请公布号 |
US5581508(A) |
申请公布日期 |
1996.12.03 |
申请号 |
US19940352619 |
申请日期 |
1994.12.09 |
申请人 |
HITACHI, LTD. |
发明人 |
SASAKI, TOSHIO;TANAKA, TOSHIHIRO;NOZOE, ATSUSHI;KUME, HITOSHI |
分类号 |
G11C11/401;G11C11/407;G11C29/00;G11C29/04;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/401 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|