发明名称 |
Apparatus and process for pattern distortion detection for semiconductor process and semiconductor device manufactured by use of the apparatus or process |
摘要 |
A finished pattern that will be formed based on a design layout pattern in a semiconductor manufacturing process is predicted, and the outline of the predicted finished pattern is converted into a polygon. On the other hand, test reference patterns are formed based on the design layout pattern. A pattern distortion in the predicted finished pattern is detected by comparing the polygonized predicted finished pattern with the test referencepatterns. In converting the predicted finished pattern into a polygon, the number of apices of the polygon is reduced. Two kinds of test reference patterns are formed: an upper limit test reference pattern obtained by reducing the design layout pattern and defining an allowable upper limit and a lower limit test reference pattern obtained by enlarging the design layout pattern and defining an allowable lower limit. |
申请公布号 |
US6343370(B1) |
申请公布日期 |
2002.01.29 |
申请号 |
US19980203582 |
申请日期 |
1998.12.02 |
申请人 |
MITSUBISHI DENKI KABUSIKI KAISHA |
发明人 |
TAOKA HIRONOBU;MORIIZUMI KOICHI |
分类号 |
H01L21/027;G01B11/16;G03F1/00;G03F1/08;G03F1/14;G03F1/68;G03F7/20;G03F7/26;(IPC1-7):G06F17/50 |
主分类号 |
H01L21/027 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|