| 发明名称 |
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| 摘要 |
A three dimensional packaging architecture for ultimate high performance computers and methods for fabricating thereof are described. The package allows very dense packaging of multiple integrated circuit chips for minimum communication distances and maximum clock speeds of the computer. The packaging structure is formed from a plurality of subassemblies. Each subassembly is formed from a substrate (8) which has on at least one side thereof at least one integrated circuit device (14, 16). Between adjacent subassemblies there is disposed a second substrate (18). There are electrical interconnection means (29) to electrically interconnect contact locations on the subassembly to contact locations on the second substrate. The electrical interconnection means can be solder mounds, wire bonds and the like. The first substrate provides electrical signal intercommunication between the electronic devices and each subassembly. The second substrate provides ground and power distribution to the plurality of subassemblies. Optionally, the outer surfaces of the structure that can be disposed a cube of memory chips. <IMAGE> |
| 申请公布号 |
JP2902937(B2) |
申请公布日期 |
1999.06.07 |
| 申请号 |
JP19940057410 |
申请日期 |
1994.03.28 |
| 申请人 |
INTAANASHONARU BIJINESU MASHIINZU CORP |
发明人 |
EUAN EZURA DEUITSUDOSON;DEUITSUDO ANDORYUU RUISU;JEEN MAAGARETSUTO SHO;ARUFURETSUDO UIIBETSUKU;JANYUSU SUTANISURO UIRUJINSUKII |
| 分类号 |
H05K3/36;H01L25/065;H05K1/05;H05K1/14;H05K3/34;H05K3/46;H05K7/14;(IPC1-7):H05K7/14 |
主分类号 |
H05K3/36 |
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