N-ARY ANALOG ADDER,申请号JP19900191797-传众专利搜索

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发明名称	N-ARY ANALOG ADDER
摘要	PURPOSE:To increase a dynamic range by adding plural n-ary analog data, subtracting a saturation value from the added value in accordance with the saturated state of the added value to compute the least significant digit(LSD) and computing a carry signal corresponding to the saturated state of the added value. CONSTITUTION:A 2nd analog circuit 2 adds plural n-ary analog data and subtracts a saturation value from the added value in accordance with a saturated state detected by the 1st analog circuit 1, so that the LSD of the added value of plural n-ary analog data can be computed. Since a 3rd analog circuit 3 outputs a carry signal corresponding to the saturated state detected by the 1st analog circuit 1, the carry of the added value of plural n-ary analog data can be computed. Consequently, the dynamic range can be increased.
申请公布号	JPH0476790(A)	申请公布日期	1992.03.11
申请号	JP19900191797	申请日期	1990.07.18
申请人	FUJITSU LTD	发明人	SATO SHINJI
分类号	G06G7/14	主分类号	G06G7/14
代理机构		代理人
主权项
地址

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