Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus

摘要

A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.

主权项

1. An imaging device comprising:
a first wafer including a pixel array having a plurality of photoelectric conversion portions and a first wiring layer; a second wafer including a second wiring layer; a third wafer including a third wiring layer; a first connection layer disposed between the first wafer and the second wafer; a second connection layer disposed between the second wafer and third wafer; a first via extending from the first wafer to the second wafer and penetrating the first connection layer; a second via disposed in the second wafer; a third via extending from the second wafer to the third wafer and penetrating the second connection layer; and a connecting portion disposed in the second wafer, wherein,
the first via includes a first point in the second wafer connected to a first region of the connecting portion,the second via includes second and third points, the second point connected to a second region of the connecting portion and the third point connected to a wiring in the second wiring layer, andthe third via includes a fourth point in the second wafer and a fifth point in the third wafer, the fourth point connected to a third region of the connecting portion and the fifth point connected to a wiring in the third wiring layer.