Highly integrated semiconductor memory device with triple well structure

摘要

A highly integrated semiconductor memory device, such as a DRAM, is provided with a unique triple-well structure which results in reduced junction capacitance of transistors and a smaller body effect. The semiconductor memory device comprises first and second wells of a first conductivity type and a third well of a second conductivity type formed in a semiconductor substrate of the first conductivity type. The first well is formed in the third well and the first well and the second well are connected to receive a ground level Vss well bias voltage and a negative level VBB well bias voltage, respectively. A plurality of MOS transistors of the first conductivity type are formed in the third well and at least two series-connected MOS transistors of the second conductivity type are formed in the first well. A plurality of MOS transistors of the second conductivity type and a plurality of memory cells are also formed in the second well.