发明名称 プロシージャからの複数のリターンターゲット制限リターン命令、プロセッサ、方法、およびシステム
摘要 A processor includes a decode unit to decode a return target restrictive return from procedure (RTR return) instruction. A return target restriction unit is responsive to the RTR return instruction to determine whether to restrict an attempt by the RTR return instruction to make a control flow transfer to an instruction at a return address corresponding to the RTR return instruction. The determination is based on compatibility of a type of the instruction at the return address with the RTR return instruction and based on compatibility of first return target restrictive information (RTR information) of the RTR return instruction with second RTR information of the instruction at the return address. A control flow transfer unit is responsive to the RTR return instruction to transfer control flow to the instruction at the return address when the return target restriction unit determines not to restrict the attempt.
申请公布号 JP5961288(B2) 申请公布日期 2016.08.02
申请号 JP20150005715 申请日期 2015.01.15
申请人 インテル・コーポレーション 发明人 カプリオリ、ポール
分类号 G06F9/42;G06F9/30;G06F9/40;G06F21/00;G06F21/52 主分类号 G06F9/42
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