| 摘要 |
PURPOSE: To achieve a DRAM adaptive to a high speed system clock by preparing an independently operative memory array in a piece of chip, controlling it by an inner RAS signal intrinsic to the array, and successively activating each RAS signal according to a system clock. CONSTITUTION: When RAS 1 becomes 'L' synchronizing with a system clock SYSC, prescribed data are outputted from one of sub-array groups 1. A signalϕSC starts sense amplifiers 101 and 102, which input the data to a shift register through I/O-S/A(71-74) started by signalϕCSI 1. Next, RAS 2 becomes 'L' synchronizing with SYC at 'H' of RAS 1 while a sub-array group 2 is being pre-charged or reset. The prescribed data are outputted from the group 2, and are inputted to a register 110 byϕCSI 2 through I/O-S/A (71-74'). Stored data are successively outputted synchronizing withϕSYSC.
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