| 摘要 |
A memory (500) for storing a plurality of words of data. Each of the words includes N data bits, where N is an integer greater than 1. The memory (500) includes a plurality of storage cells, each of the word storage cells having N + 1 single bit memory cells (512, 513, 514, 517). The single bit memory cells (512, 513, 514, 517) are numbered from 1 to N + 1. Each of the single bit memory cells (512, 513, 514, 517) connects a conductor in a word bus common to all of the memory cells in that word to a bit line that is connected in common to all of the single bit memory cells (512, 513, 514, 517) having the same number. The word bus also includes a conductor for transmitting a signal indicating that this connection is to be made. Each of the single bit memory cells (512, 513, 514) having a number between 1 and N stores one of the N data bits. The memory (500) also includes N sense amplifiers (550, 560, 570), one of the sense amplifiers (550, 560, 570) being connected to each of the bit lines to which the bits numbered 1 to N are connected. Each of the sense amplifiers (550, 560, 570) compares a signal on the bit line (551-553) connected thereto to a signal on the bit line (557) connected to the single bit memory cells (517) numbered (N + 1). When data is written into the data bits of the word, a predetermined value is preferably written into the single bit memory cell (517) number N + 1. Embodiments of the present invention based on ferroelectric FET memory cells (10) or ferroelectric capacitor-based memory cells (100) are preferred.
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