发明名称 Sequence-based verification method and system
摘要 A hardware verification method includes obtaining a set of packets to be driven by a device under test and obtaining a set of timing and relation criteria which determines a sequence in which the packets should be driven by the device under test. The method further includes starting multiple drive loops, each drive loop picking up a packet and forcing the device under test to drive the packet. The method further includes starting multiple expect loops, each expect loop determining when to expect a packet driven by the device under test and picking up the expected packet when it arrives. For each drive loop, the method confirms that the timing and relation criteria are satisfied prior to allowing the drive loop to force the device under test. For each expect loop, the method checks if the expected packet arrives within a specified time period and raises an error flag if the expected packet does not arrive within the specified time period.
申请公布号 US2002095634(A1) 申请公布日期 2002.07.18
申请号 US20010765478 申请日期 2001.01.18
申请人 BHASIN SUDHIR;BACHINA ANU 发明人 BHASIN SUDHIR;BACHINA ANU
分类号 G01R31/28;G06F7/02;G06F11/00;(IPC1-7):G01R31/28 主分类号 G01R31/28
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